Electrostatic discharges (ESDs) are high-voltage spikes of static charges which damage modern integrated circuits. ESDs are a significant failure mechanism, particularly as integrated circuit physical dimensions continue to shrink to the deep quarter-micron range.
Electrically, an ESD occurs upon contact of one or more of the terminals of an integrated circuit with a body or material that is statically charged to a high voltage. This level of static charge is readily generated by the triboelectric effect, and other mechanisms acting upon humans, equipment, or the circuits themselves. Upon contact, the integrated circuit discharges through its active devices and DC current paths. If the amount of charge is excessive however, the discharge current density can permanently damage the integrated circuit so that it is no longer functional or so that it is more prone to later-life failure. ESD damage thus is a cause of yield loss in manufacturing and also poor reliability in use.
In the past, n-type metal oxide semiconductor (NMOS) transistors have been widely used as the primary component in ESD protection circuits in semiconductor integrated circuit devices. Under ESD stress conditions, the NMOS transistor behavior changes drastically from normal operation. The actual conduction mechanism is that of bipolar action in the parasitic lateral bipolar structure.
In advanced manufacturing processes with transistors having lightly doped drain (LDD) junctions, the NMOS performance is limited because the peak heating occurs close to the surface, which has poor thermal conductivity. Therefore, an ESD implant has to be used to make the junction deeper as well as to overdope the lightly doped region of the LDD for improved ESD performance.
It is also well known that salicidation (self-aligned siliciding) of the drain and source junctions reduces ESD performance significantly due to discharge current localization. From the ESD viewpoint, the primary effect of the salicidation is to bring a transistor drain or a source contact closer to its diffusion edge near their respective gate edge. The consequence is that under high current conditions, the ballasting resistance between the drain or the source contact and their respective gate edge is reduced and the short current path cause “hot spot” formation, usually at the gate edge. Once a hot spot is formed, there is very little resistance to prevent current localization through the hot spot and so most of the current flows through the silicide to the gate edge. This leads to higher power dissipation and damage in this region. Also, the high power dissipation through the drain or source silicide can cause damage at the drain or source contact when the eutectic temperature is exceeded.
The most conventional solution to the salicidation problem is called a “salicide block”. Most salicidation fabrication technology processes have a “salicide block” option, which is an additional photolithographic process step to block the formation of silicide in areas close to a transistor's gate edge. Without the gate edge silicide, an ESD implantation is required make the drain junction deeper as well as to overdope the lightly doped region of the LDD for better ESD performance. Since the ESD implantation is undesirable in the circuitry being protected, an ESD implant block would be required over the non-ESD circuitry. Thus, this approach adds to process complexity because it requires at least two additional photolithographic process steps; i.e., the silicide block and the ESD implant block.
In the parasitic lateral bipolar structure of the NMOS transistor, the majority of the electrons reaching the collector junction are emitted from the emitter junction sidewall, which results in a very small “intrinsic” base area. The high current is confined to a very small region of the emitter and base regions that will lead to a large power density in these regions and hence higher temperatures.
Substrate current initially needs to forward-bias a small region of the source-substrate junction to turn-on the bipolar action. However, for better ESD performance, a larger emitter area is preferred. This will be particularly effective if the source barrier lowering occurs deeper in the junction, allowing the power dissipation to take place deeper in the device to reduce the temperature rise in the device.
One normal way to provide ESD protection is to use a grounded gate thin oxide n-type MOS (GGNMOS) transistor. In the GGNMOS transistor, the voltage necessary to turn the transistor on (the turn-on voltage) is reached by the occurrence of an avalanche breakdown. Unfortunately, as these transistors continue to shrink in size down to the deep-quarter-micron geometry level, the avalanche breakdown becomes so high that the gate oxide breakdown voltage approaches the turn-on voltage. Thus, the protection window tends to go to zero and at a small enough geometry will provide no protection at all.
Briefly, there are a large number of issues related to ESD protection structures. Is it possible to remove or reduce the ESD process steps for reducing process cost? Is it possible to reduce the ESD adjustment cycle time or make the ESD adjustment flexible process? Is it possible to increase the parasitic “intrinsic” emitter area and make the source barrier flowing occur deeper in the junction? Can the thin oxide for ESD reliability be removed while making the structure easily turned on? Is it possible to reduce the trigger-on voltage of the structure?
It is critical that a new form of ESD protection structure be developed which provides solves the above questions in order to progress to smaller integrated circuit geometries that are compatible with saliciding technology without adding process complexity or cost.